Analog In-Memory Computing NPU
Heterogeneous embedded NPU combining PCM-based analog in-memory computing tiles with digital accelerators for efficient neural network inference.
Heterogeneous embedded NPU combining PCM-based AIMC tiles with digital accelerators (DPU, RISC-V) via 2D mesh interconnect. All MobileBERT weights are stored on-chip.
Specifications:
- ~30 mm² on 28 nm FD-SOI
- <1 W average power
- Competitive with high-end mobile SoCs
Publication: Boybat-Kara I, Boesch T, et al. Heterogeneous Embedded Neural Processing Units Utilizing PCM-based Analog In-Memory Computing. IEDM 2024 (Invited paper).